1. Field of the Invention
The present invention relates to a novel structure of semiconductor crystals. More particularly, it relates to an improved structure of III-V compound semiconductors having controlled piezoelectric property. The semiconductor structure according to the present invention is useful for fabricating elements such as MESFET, IIBT, laser diodes or the like.
The present invention relates also to a process for producing such a novel structure of semiconductor crystals.
2. Description of the Related Art
III-V compound semiconductors having a zincblende type crystalline structure such as gallium arsenide (GaAs), indium phosphite (InP) or the like are used as a material for high-speed switching devices or high-frequency amplifying devices owing to their high electron mobility and as a material for light-emitting devices owing to their direct transition type band structure.
FIG. 1 illustrates an example of a well-known Schottky barrier type field-effect transistor fabricated on a GaAs substrate. In the GaAsMESFET, an active channel layer 24 is formed by ion implantation technique or the like on a semi-insulating GaAs (100) substrate 14 which is sliced out of an ingot which is prepared by the Czochralski technique. A gate electrode 34, a source electrode 44 and a drain electrode 54 are formed and then a protective coating layer 64 made of insulator such as SiO.sub.2 is deposited thereon.
In the conventional GaAs metal-semiconductor field effect transistor (MESFET) above-mentioned, elastic stresses are generated in the GaAs substrate because of difference in thermal expansion coefficient between the gate metal and the GaAs which has noncontrosymmetric and polar properties and because of the influence from the protective overlay and the ohmic electrodes. These stresses induce a charge due to the piezoelectric effect.
Such a charge induced by the piezoelectric effect causes a trouble in the uniformity of electrical characteristics of MESFETs fabricated, because the drain current of the MESFET drifts and/or the threshold voltage shifts. The charges induced by the piezoelectric effect arouse another problem of anisotropy that the electric characteristics depend on the orientation of the gate electrode of MESFET. This fact was reported by M. F. Chang et al. in "Appl. Physi. Lett." 45 (3) 1, Aug. 1984 p 279 and by T. Ohnishi et al. in "IEEE Electron Device Letters" Vol. EDL-6 No. 4, April 1985.
In the prior arts, in order to overcome these problems, it is proposed to select materials and thickness of the gate electrode and of the protective overlay in order to minimize the stresses (P. M. Asbeck et al. in "IEEE Transactions on Electron Devices" Vol. ED-31 No. 10, October, 1984). The selection of materials and thickness of the gate electrode and of the protective overlay is, however, limited. Therefore, there has been a strong demand to solve the problems much basically by changing the physical properties of the semiconductor materials themselves.
Technological trend in GaAsMESFET is to reduce the gate length so as to improve its performance. However, as the gate length is reduced, a so called short-channel effect appears so that leakage of electrons out of a channel region increases and the device characteristics of a short channel FET deviates from a device whose gate length is long. If a FET having such short-channel effect is built in an integrated circuit, the variation in the electrical characteristics become uncontrollable with respect to the variation in gate length but the device parameters are influenced directly by manufacturing conditions such as gate processing, so that it becomes difficult to design the circuits.
A method for controlling the short-channel effect to improve the performance of GaAsMESFET is reported by T. Onodera et al. in "IEEE Transaction on Electron devices" Vol. ED-32, No. 11, November 1985, p.2314. In this paper, the magnitude of stress exerted to the GaAs substrate caused by a protective dielectric overlay is modified by changing the thickness of the overlay in such manner that a piezoelectric charge which is desirable to improve the performance can be induced. However, application of this technique is limited because the thickness of the protective overlay and hence the stress induced by the protective overlay depend on the other factors such as wiring process or the like, so that the design flexibility is restricted in this technique.
Basic logic elements used in the GaAs integrated circuit built on a GaAs substrate are DCFL (Direct Coupled FET Logic), BFL (Buffered FET Logic), SCFL (Source Coupled FET Logic) or the like. Among them, DCFL and SCFL are fabricated by different FETs each having its own threshold voltage on a common substrate. In the prior art, when such different FETs are fabricated on a common substrate, it is necessary to prepare different n-type channels each having a different carrier density or a different thickness, so that a plurality of operations are required to prepare the different channels, with the result that the manufacturing process becomes intricate.
Japanese patent laid-open No. 60-176,276 utilizes the above-mentioned anisotropy or the piezoelectric charge in the fabrication of an integrated circuit. Namely, in this patent, two FETs having two different threshold voltages are built on a common substrate by changing the orientation of gate electrodes for respective channels each possessing an identical concentration and an identical thickness without increasing the channel forming steps.
However, the value of the piezoelectric charge which results in the difference between two threshold voltages is determined by a piezoelectric constant which is inherent in material of the substrate used if the magnitude of the stress applied to the substrate is constant, so that it is impossible to obtain controllably a desired value of the threshold voltage.